This invention relates to timing circuits for electronic data processing systems. In the past, the operation of electronic data processing systems such as computers, numerically controlled machine tools, and the like, have been controlled by clock circuits which generate periodic clock pulses having a fixed period. However, the use of fixed clock periods have several serious drawbacks. First, if two or more digital devices or circuits, one or both of which has an independent internal clock, are interfaced with each other, the interacting signals must be synchronized with one or both clocks. Synchronizing logic is necessary and is usually complex and expensive. Next, the synchronizing operation is time-consuming and therefore does not allow the two devices to run as fast as possible. Finally, in a digital circuit or data processing system having a fixed period clock circuit, the response time of the devices may not be in increments of the fixed clock period and this introduces inefficiency. In the program steps which are completed before the end of a fixed timing period, the computer is idle during the subsequent portion of the timing period, since the next step cannot commence until the next clock pulse is generated. Thus, a fixed timing period causes an inherent time loss in a data processing system which can be substantial when the system devices are not perfectly matched to the system clock. Also, even if the devices are perfectly matched to the clock, subsequent changes or additions to the system may upset the match and introduce inefficiency.